--
-- VHDL Architecture Fietssimulator_lib.char2time.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp6241)
--          at - 16:57:02 14-04-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY s_char2time IS
  PORT( 
  char    : IN     STD_LOGIC_VECTOR(7 DOWNTO 0);
  strb    : IN     STD_LOGIC;
  clk     : IN     STD_LOGIC;
  rst     : IN     STD_LOGIC;
  X       : OUT    STD_LOGIC;
  hex     : OUT    STD_LOGIC;
  eos     : IN     STD_LOGIC;
  load    : BUFFER STD_LOGIC;
  clear   : BUFFER STD_LOGIC;
  h0      : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
  h1      : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
  h2      : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
  h3      : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
  time    : BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0);
  delta_t : OUT    INTEGER RANGE 0 TO 65535
  );
END ENTITY s_char2time;

--
ARCHITECTURE v OF s_char2time IS

SIGNAL bin    : STD_LOGIC_VECTOR(3 DOWNTO 0);



BEGIN
  
  
  PROCESS(char)
    BEGIN
      
      IF char = x"58" THEN
        X <= '1';
      ELSE 
        X <= '0';
      END IF;
      
      IF   char <= x"39" THEN
        bin <= char(3 DOWNTO 0);
      ELSE
        bin <= char(3 DOWNTO 0) + "1001";
      END IF;
      
      IF ((char >= x"30") AND (char <= x"39")) OR ((char >= x"41") AND (char <= x"46")) THEN
        hex <= '1';
      ELSE 
        hex <= '0';
      END IF;
      
    END PROCESS;
    
    
    PROCESS(rst, clk)
      BEGIN
        IF rst = '1' THEN
          h0 <=  "0000";
          h1 <=  "0000";
          h2 <=  "0000";
          h3 <=  "0000";
        ELSIF RISING_EDGE(clk) THEN
          
          IF strb = '1' THEN
            h0 <=  bin;
            h1 <=  h0;
            h2 <=  h1;
            h3 <=  h2;
          END IF;
          
          
        END IF;
      END PROCESS;
      
      
      
      
      
      PROCESS(rst, clk)
        BEGIN
          IF rst = '1' THEN
            
            time <=  x"FFFF";
            
          ELSIF RISING_EDGE(clk) THEN
            
            IF clear = '1' THEN
              time <= x"FFFF";
            ELSIF load = '1'THEN
               time <= h3 & h2 & h1 & h0;
            END IF;
            
            
          END IF;
        END PROCESS;
        
        
        load  <= '1' WHEN (eos = '1') AND (h3 & h2 & h1 & h0 /= x"0000" ) ELSE
                 '0'; 
        
        
        delta_t <= CONV_INTEGER(time);
        
        
        
        PROCESS(rst, clk)
          BEGIN
            IF rst = '1' THEN
              
              clear <=  '0';
              
            ELSIF RISING_EDGE(clk) THEN
              
              IF (eos = '1') AND (h3 & h2 & h1 & h0  = x"0000" ) THEN
                clear <= '1';
              ELSIF load = '1'THEN
                clear <= '0';
              END IF;
              
              
            END IF;
          END PROCESS; 
          
       
        
        
      END ARCHITECTURE v;
      
      
      
      
      
      
      
      
      